Negative slacks are still negative even though some of them become smaller. I have a feeling that adding these constraints does not help a lot on solving negative slacks. Add timing constraint and try to solve negative slacks:īy referring to the SDI user guide appendix A and the SDC file in Altera reference design, I add some timing constraints such as set_clock_groups and set_false_path. I'm not sure if I used them correctly.Ģ). I keep the post-fit netlist of SDI transceiver in design partition window and fix its location and size in logiclock window in order to preserve its performance.ĭesign partition and logiclock are quite new things to me. Once I have a good compilation result which passes my basic test for rx ability. I separate this design into the SDI transceiver and a qsys which includes video processing IPs in design partition. I'm trying two ways to solve my problem, but they all fail. This situation really troubles me because I don't want to compile my design for several times until I get a good rx ability for the SDI transceiver.
My problem is my design cannot always have good rx ability after each compilation.įor example, the SDI transceiver sometimes cannot be frame locked for a video standard after I only change some parameters in a video processing IP.
My design has a triple SDI transceiver and several video processing IPs.Ī basic test for this design is to use video standards of SDI (487i, 576i, 720p, 1080i, and 1080p) as input and to see if the SDI receiver is alignment locked, TRS locked, and frame locked in the signal of rx_status.
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